Inter-chip communication provides the signaling between components of computing systems. A transmitting device sends a signal or bit pattern to a receiving device. Data bus inversion has traditionally been used to minimize the number of one or zeros transferred over a data bus. Bus inversion refers to inverting every bit on a bus prior to transmission. Such an inverted bus is accompanied by a bit or signal indicating that the bus has been inverted, which allows the receiving device to appropriately interpret the received data. Such a concept has been further extended to buses other than the data bus, and will be referred to generally herein as dynamic bus inversion (DBI), which can include any collection or group of signal lines, including one or more buses. As mentioned, DBI has been used to invert a signal line group to minimize the number of bits that have a specified logic level. For example, if the transmitting device seeks to minimize the number of ones sent, then for a group of signal lines that has more ones than zeros, the transmitting device can invert the signal lines and generate an inversion indication. The same can be accomplished in reverse for a transmitting device seeking to minimize the number of zeros.
An extended use of DBI involves minimizing the switching of signals in the signal line group. In such a use, instead of determining if there are more ones or zeros and inverting the signal line group to minimize the desired logic state, the transmitting device can determine if the output bit pattern will toggle more signal lines than signal lines that will remain the same. Thus, if the output bit pattern has more transitions from zero-to-one or one-to-zero than signal lines that will transmit the same logic value as a previous transmission, the transmitting device can invert the bus and generate the inversion indication. Such an operation can reduce the number of toggles in the group of signal lines for consecutive transmissions.
However, as power consumption considerations increase in importance in modern electronics with lower voltages and tighter power budgets while transfer speeds increase, DC (direct current) balance in inter-chip communication becomes a performance factor of interest. DBI looks only at two consecutive transmissions, determining what to transmit in the current transaction based on the immediately preceding transaction. Depending on the signals transferred, DBI can actually degrade DC balance on the signal line group. For example, consider an 8 bit bus where the transmitting device seeks to minimize the number of ones. If more than 4 of the bits are ones, the transmitting device will invert the bus and send more than 4 zeros. In either case there is not DC balance on the bus.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.